Method and system for filter calibration using fractional-n frequency synthesized signals

ABSTRACT

A method and system for filter calibration using fractional-N frequency synthesized signals are presented. Aspects of the method may include generating an LO signal by a PLL circuit within a chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. A frequency response for a filter circuit integrated within the chip may be calibrated by adjusting parameters associated with the filter circuit based on the generated LO signal. Aspects of the system may include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The frequency response may be calibrated by adjusting the filter based on the generated reference signal.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to, claims priority to, and claims thebenefit of:

U.S. Provisional Application Ser. No. 60/778,232, filed on Mar. 2, 2006.

This application also makes reference to:

U.S. application Ser. No. ______ (Attorney Docket 17540US02) filed oneven date herewith;U.S. application Ser. No. 11/385,390 filed on Mar. 21, 2006; andU.S. application Ser. No. 11/385,389 filed on Mar. 21, 2006.

Each of the above stated applications is hereby incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to on-chip RF tuners. Morespecifically, certain embodiments of the invention relate to a methodand system for filter calibration using fractional-N frequencysynthesized signals.

BACKGROUND OF THE INVENTION

Broadcasting and telecommunications have historically occupied separatefields. In the past, broadcasting was largely an “over-the-air” mediumwhile wired media carried telecommunications. That distinction may nolonger apply as both broadcasting and telecommunications may bedelivered over either wired or wireless media. Present development mayadapt broadcasting to mobility services. One limitation has been thatbroadcasting may often require high bit rate data transmission at rateshigher than could be supported by existing mobile communicationsnetworks. However, with emerging developments in wireless communicationstechnology, even this obstacle may be overcome.

Terrestrial television and radio broadcast networks have made use ofhigh power transmitters covering broad service areas, which enableone-way distribution of content to user equipment such as televisionsand radios. By contrast, wireless telecommunications networks have madeuse of low power transmitters, which have covered relatively small areasknown as “cells”. Unlike broadcast networks, wireless networks may beadapted to provide two-way interactive services between users of userequipment such as telephones and computer equipment.

The introduction of cellular communications systems in the late 1970'sand early 1980's represented a significant advance in mobilecommunications. The networks of this period may be commonly known asfirst generation, or “1G” systems. These systems were based upon analog,circuit-switching technology, the most prominent of these systems mayhave been the advanced mobile phone system (AMPS). Second generation, or“2G” systems, ushered improvements in performance over 1G systems andintroduced digital technology to mobile communications. Exemplary 2Gsystems include the global system for mobile communications (GSM),digital AMPS (D-AMPS), and code division multiple access (CDMA). Many ofthese systems have been designed according to the paradigm of thetraditional telephony architecture, often focused on circuit-switchedservices, voice traffic, and supported data transfer rates up to 14.4kbits/s. Higher data rates were achieved through the deployment of“2.5G” networks, many of which were adapted to existing 2G networkinfrastructures. The 2.5G networks began the introduction ofpacket-switching technology in wireless networks. However, it is theevolution of third generation, or “3G” technology that may introducefully packet-switched networks, which support high-speed datacommunications.

Standards for digital television terrestrial broadcasting (DTTB) haveevolved around the world with different systems being adopted indifferent regions. The three leading DTTB systems are, the advancedstandards technical committee (ATSC) system, the digital video broadcastterrestrial (DVB-T) system, and the integrated service digitalbroadcasting terrestrial (ISDB-T) system. The ATSC system has largelybeen adopted in North America, South America, Taiwan, and South Korea.This system adapts trellis coding and 8-level vestigial sideband (8-VSB)modulation. The DVB-T system has largely been adopted in Europe, theMiddle East, Australia, as well as parts of Africa and parts of Asia.The DVB-T system adapts coded orthogonal frequency division multiplexing(COFDM). The OFDM spread spectrum technique may be utilized todistribute information over many carriers that are spaced apart atspecified frequencies. The OFDM technique may also be referred to asmulti-carrier or discrete multi-tone modulation. This technique mayresult in spectral efficiency and lower multi-path distortion, forexample. The ISDB-T system has been adopted in Japan and adaptsbandwidth segmented transmission orthogonal frequency divisionmultiplexing (BST-OFDM). The various DTTB systems may differ inimportant aspects; some systems employ a 6 MHz channel separation, whileothers may employ 7 MHz or 8 MHz channel separations.

While 3G systems are evolving to provide integrated voice, multimedia,and data services to mobile user equipment, there may be compellingreasons for adapting DTTB systems for this purpose. One of the morenotable reasons may be the high data rates that may be supported in DTTBsystems. For example, DVB-T may support data rates of 15 Mbits/s in an 8MHz channel in a wide area single frequency network (SFN). There arealso significant challenges in deploying broadcast services to mobileuser equipment. Because of form factor constraints, many handheldportable devices, for example, may require that PCB area be minimizedand that services consume minimum power to extend battery life to alevel that may be acceptable to users. Another consideration is theDoppler Effect in moving user equipment, which may cause inter-symbolinterference in received signals. Among the three major DTTB systems,ISDB-T was originally designed to support broadcast services to mobileuser equipment. While DVB-T may not have been originally designed tosupport mobility broadcast services, a number of adaptations have beenmade to provide support for mobile broadcast capability. The adaptationof DVB-T to mobile broadcasting is commonly known as DVB handheld(DVB-H). The broadcasting frequencies for Europe are in UHF (bands IVN)and in the US, the 1670-1675 MHz band that has been allocated for DVB-Hoperation. Additional spectrum is expected to be allocated in the L-bandworld-wide.

To meet requirements for mobile broadcasting the DVB-H specificationsupports time slicing to reduce power consumption at the user equipment,addition of a 4K mode to enable network operators to make tradeoffsbetween the advantages of the 2K mode and those of the 8K mode, and anadditional level of forward error correction on multi-protocolencapsulated data—forward error correction (MPE-FEC) to make DVB-Htransmissions more robust to the challenges presented by mobilereception of signals and to potential limitations in antenna designs forhandheld user equipment. DVB-H may also use the DVB-T modulationschemes, like QPSK and 16-quadrature amplitude modulation (16-QAM).

While several adaptations have been made to provide support for mobilebroadcast capabilities in DVB-T, concerns regarding device size, cost,and/or power requirements still remain significant constraints for theimplementation of handheld portable devices enabled for digital videobroadcasting operations. For example, typical DVB-T tuners or receiversin mobile terminals may employ super-heterodyne architectures with oneor two intermediate frequency (IF) stages and direct sampling of thepassband signal for digital quadrature down-conversion. Moreover,external tracking and SAW filters may generally be utilized for channelselection and image rejection. Such approaches may result in increasedpower consumption and high external component count, which may limittheir application in handheld portable devices. As a result, the successof mobile broadcast capability of DVB-T may depend in part on theability to develop TV tuners that have smaller form factor, are producedat lower cost, and consume less power during operation. Furthermore,process and temperature variations within conventional tuners orreceivers in mobile terminals result in deviation in the characteristicsof many sub-circuits of the transceiver. A very important case is thedeviation of the frequency response of analog filters used within thetuners or receivers. Such deviation of the frequency response results indeterioration of channel selection capabilities of the tuners orreceivers.

As mobile terminals support a wider range of content from voice to datato video, they may be required to receive a correspondingly wider rangeof frequencies. Consequently, filtering circuitry may be required tofilter signals for correspondingly wider ranges of frequencies.

FIG. 1 is diagram for a conventional filter calibration scheme utilizinga matched oscillator. This is an indirect filter calibration techniques,meaning that filter bandwidth is calibrated through the calibration of acircuit other than the filter itself (the oscillator). Referring to FIG.1, there is shown a filter 202, an oscillator 204, a crystal oscillator206, a frequency divider block 208, an exclusive-or (XOR) block 210, anda control block 212.

The oscillator 204 may comprise suitable logic, circuitry, and/or codethat may enable generation of a clock signal. The oscillator 204 maycomprise resistive (R) and capacitive (C) components. The R and Ccomponents may be variable or fixed. When the frequency associated withthe clock signal is based on the values for the R and C components, theoscillator 204 may comprise an RC oscillator circuit.

The oscillator 204 may comprise active components, for exampleoperational amplifier (op-amp) and C components. The op-amp componentmay comprise one or more electrical devices characterized by one or moretransconductance (G_(m)) values. The C component may comprise one ormore electrical devices characterized by one or more fixed or variablecapacitive values. When the frequency associated with the clock signalis based on the values for the op-amp and C components, the oscillator204 may comprise a G_(m)C oscillator circuit.

The frequency divider block 208 may comprise suitable logic, circuitry,and/or code that may enable generation of an output signal based on aninput signal, wherein the input signal is characterized by a frequencythat is a multiple of the corresponding frequency of the output signal.The value of each corresponding frequency may be determined by thefrequency divider block 208.

The XOR block 210 may comprise suitable logic, circuitry, and/or codethat may enable generation of an output signal in which the value of theoutput signal is based on a comparison of respective values associatedwith two input signals. The XOR block 210 may output a LOW value whenthe respective values of the two input signals are approximately equal.The XOR block 210 may output a HIGH value when the respective values ofthe two input signals are not approximately equal.

The control block 212 may comprise suitable logic, circuitry, and/orcode that may enable generating a control signal, f_(Control), based onan input signal. The control signal may comprise an analog signal, suchas a value for a voltage or a current for example, based on the inputsignal. The control signal may comprise a digital representationcomprising one or more bits for example, based on the input signal. Thecontrol block 212 may receive an input signal from an external circuit.The control block 212 may generate the control signal based on the inputsignal. The control signal may be communicated to control at least aportion of the circuitry from which the input signal was received.

In operation, the crystal oscillator 206 may enable generation of acrystal (xtal) timing signal. The crystal timing signal may becharacterized by a crystal frequency, f_(Xtal). The frequency divider208 may receive the crystal timing signal as an input signal. Thefrequency divider 208 may utilize a frequency division factor, f_(p), togenerate a reference timing signal characterized by a referencefrequency, f_(Ref), and a reference phase φ_(Ref). The value of thereference frequency may be about equal to the ratio of the value of thereference frequency and the value of the frequency division factor,f_(Ref)/f_(D).

The oscillator 204 may enable generation of an oscillator timing signalcharacterized by an oscillator frequency, f_(Osc), and an oscillatorphase φ_(Osc). For an oscillator 204 comprising an RC oscillator, theoscillator frequency may be referred to as an RC oscillator frequency,f_(Osc)(RC). The corresponding oscillator phase may be referred to as anRC oscillator phase, φ_(Osc)(RC). The value of the RC oscillatorfrequency and/or phase may be based on values for the R and Ccomponents. The values for the R and/or C components may be determinedbased on the control signal f_(Control).

The XOR block 210 may concurrently compare a value for the referencetiming signal and a corresponding value for the oscillator timing signalat various time instants. Based on the comparison, the XOR block 210 maygenerate a difference signal. The difference signal may be nonzero whenthere are differences between the frequencies f_(Ref) and f_(Osc)(RC),at a given time instant. The difference signal may be nonzero when thereare differences between the phases φ_(Ref) and φ_(Osc)(RC), at a giventime instant.

The control block 212 may receive the difference signal and generate thecontrol signal, f_(Control), based on the value of the differencesignal. The control block 212 may communicate the control signal,comprising feedback information, to the oscillator 204. The feedbackinformation may cause the oscillator 204 to adjust the R and/or Cvalues. As a result of the adjustment, the corresponding frequencyand/or phase values, f_(Osc)(RC)/φ_(Osc)(RC), may be adjusted.

For an oscillator 204 comprising an G_(m)C oscillator, the oscillatorfrequency may be referred to as an G_(m)C oscillator frequency,f_(Osc)(G_(m)C). The corresponding oscillator phase may be referred toas an G_(m)C oscillator phase, φ_(Osc)(G_(m)C). The value of the G_(m)Coscillator frequency and/or phase may be based on values for the op-ampand C components. The values for the op-amp and/or C components may bedetermined based on the control signal f_(Control).

The difference signal generated by the XOR block 210 may be nonzero whenthere are differences between the frequencies f_(Ref) andf_(Osc)(G_(m)C), at a given time instant. The difference signal may benonzero when there are differences between the phases φ_(Ref) andφ_(Osc)(G_(m)C), at a given time instant.

The control block 212 may receive the difference signal and generate thecontrol signal, f_(Control), based on the value of the differencesignal. The control block 212 may communicate the control signal,comprising feedback information, to the oscillator 204. The feedbackinformation may cause the oscillator 204 to adjust the G_(m) and/or Cvalues. As a result of the adjustment, the corresponding frequencyand/or phase values, f_(Osc)(G_(m)C)/φ_(Osc)(G_(m)C), may be adjusted.

The oscillator 204 may utilize shared or common components with thefilter 202. For example, for an oscillator 204 that comprises R and Ccomponents, the filter 202 may comprise equivalent R and C components.When the value for the f_(−3dB) filter cut-off frequency is based on thevalues of the R and C components, the filter 202 may comprise an RCfilter circuit. For an oscillator 204 that comprises op-amp componentsand C components, the filter 202 may comprise equivalent op-amp and Ccomponents. When the value for the f_(−3dB) filter cut-off frequency isbased on the values of the op-amp and C components, the filter 202 maycomprise a G_(m)C filter circuit.

For a filter 202 comprising an RC filter circuit, the control signal,f_(Control), generated by the control block 212 may cause the filter 202to adjust the R and/or C values for the equivalent R and/or Ccomponents. As a result of the adjustment, the corresponding value forthe f_(−3dB) filter cut-off frequency may be adjusted. For a filter 202comprising a G_(m)C filter circuit, the control signal, f_(Control),generated by the control block 212 may cause the filter 202 to adjustthe G_(m) and/or C values for the equivalent op-amp and/or C components.As a result of the adjustment, the corresponding value for the f_(−3dB)filter cut-off frequency may be adjusted.

The oscillator 204 may be utilized to calibrate the filter 202 since thecontrol signal, f_(Control), is generated based on the oscillatorfrequency f_(Osc), and/or oscillator phase φ_(Osc). The control signalmay cause the filter 202 to compute a value for the f_(−3dB) filtercut-off frequency. A disadvantage in this method is that the accuracy ofthe calibration may be limited based on the extent to which the valuesfor the R and C components in the oscillator 204 are equal tocorresponding values for the equivalent R and C components in the filter202, for a given value of the control signal f_(Control). The accuracyof the calibration may also be limited based on the range of values forfrequency, f_(Ref), and/or phase, φ_(Ref), which may be generated by thefrequency divider block 208.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with some aspects of the present invention asset forth in the remainder of the present application with reference tothe drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for filter calibration usingfractional-N frequency synthesized signals, substantially as shown inand/or described in connection with at least one of the figures, as setforth more completely in the claims.

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is diagram for a conventional filter calibration scheme utilizinga matched oscillator.

FIG. 2A is a block diagram illustrating an exemplary mobile terminal, inaccordance with an embodiment of the invention.

FIG. 2B is a block diagram illustrating exemplary communication betweena multi-band RF receiver and a digital baseband processor in a mobileterminal, in accordance with an embodiment of the invention.

FIG. 2C is a block diagram illustrating an exemplary single-chipmulti-band RF receiver with an integrated LNA in each front-end, inaccordance with an embodiment of the invention.

FIG. 2D is a diagram for an exemplary direct filter calibration schemeutilizing filtering, which may be utilized in connection with anembodiment of the invention.

FIG. 3A is a block diagram of an exemplary analog baseband processingsystem supporting auto-calibration, in accordance with an embodiment ofthe invention.

FIG. 3B is a schematic diagram of an exemplary opamp-RC baseband filterthat may be used in accordance with an embodiment of the invention.

FIG. 3C is a block diagram of an exemplary baseband processing systemusing opamp-RC filters and an auto-calibration loop, in accordance withan embodiment of the invention.

FIG. 4 is a flow diagram illustrating exemplary steps in a filtercalibration scheme using fractional-N frequency synthesized signals, inaccordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention provide a method and system for filtercalibration using fractional-N frequency synthesized signals. Aspects ofthe method may comprise generating a LO signal by a PLL circuit within achip. A reference signal may be generated based on the generated LOsignal and a synthesizer control signal. The method may further comprisecalibrating a frequency response for a filter circuit integrated withinthe chip by adjusting parameters associated with the filter circuitbased on the generated reference signal. Aspects of the system mayinclude a single-chip multi-band RF receiver that enables generation ofa LO signal by a PLL circuit within the single-chip. A reference signalmay be generated based on the generated LO signal and a synthesizercontrol signal. The single-chip multi-band RF receiver may enablecalibration of a frequency response for a filter circuit integratedwithin the chip. The frequency response may be calibrated by adjustingthe filter based on the generated reference signal.

Various embodiments of the invention may comprise a scheme forcalibrating a filter in a communication receiver without requiringadditional circuitry. In such embodiments, a Σ−Δ fractional-Nsynthesizer may be utilized for synthesizing RF signals. The Σ−Δfractional-N synthesizer may enable the generation of a wide range ofreference signal frequencies. In addition, the Σ−Δ fractional-Nsynthesizer may enable more accurate generation of a specified filtercutoff frequency f_(−3dB) than may be the case with many conventionalfilter calibration schemes. Various embodiments of the invention mayutilize a digital frequency synthesizer to enable even greater accuracyin the generation of a specific frequency f_(−3dB).

FIG. 2A is a block diagram illustrating an exemplary mobile terminal, inaccordance with an embodiment of the invention. Referring to FIG. 2A,there is shown a mobile terminal 120 that may comprise an RF receiver123 a, an RF transmitter 123 b, a digital baseband processor 129, aprocessor 125, and a memory 127. A receive antenna 121 a may becommunicatively coupled to the RF receiver 123 a. A transmit antenna 121b may be communicatively coupled to the RF transmitter 123 b. The mobileterminal 120 may be operated in a system, such as the cellular networkand/or digital video broadcast network described in FIG. 2A, forexample.

The RF receiver 123 a may comprise suitable logic, circuitry, and/orcode that may enable processing of received RF signals. The RF receiver123 a may enable receiving RF signals in a plurality of frequency bands.For example, the RF receiver 123 a may enable receiving DVB-Htransmission signals via the VHF band, from about 174 MHz to about 240MHz, the UHF band, from about 470 MHz to about 890 MHz, the 1670-1675MHz band, and/or the L-band, from about 1400 MHz to about 1700 MHz, forexample. Moreover, the RF receiver 123 a may enable receiving signals incellular frequency bands, for example. Each frequency band supported bythe RF receiver 123 a may have a corresponding front-end circuit forhandling low noise amplification and down conversion operations, forexample. In this regard, the RF receiver 123 a may be referred to as amulti-band receiver when it supports more than one frequency band. Inanother embodiment of the invention, the mobile terminal 120 maycomprise more than one RF receiver 123 a, wherein each of the RFreceivers 123 a may be a single-band or a multi-band receiver.

The RF receiver 123 a may quadrature down convert the received RF signalto a baseband frequency signal that comprises an in-phase (I) componentand a quadrature (Q) component. The RF receiver 123 a may perform directdown conversion of the received RF signal to a baseband frequencysignal, for example. In some instances, the RF receiver 123 a may enableanalog-to-digital conversion of the baseband signal components beforetransferring the components to the digital baseband processor 129. Inother instances, the RF receiver 123 a may transfer the baseband signalcomponents in analog form.

The digital baseband processor 129 may comprise suitable logic,circuitry, and/or code that may enable processing and/or handling ofbaseband frequency signals. In this regard, the digital basebandprocessor 129 may process or handle signals received from the RFreceiver 123 a and/or signals to be transferred to the RF transmitter123 b, when the RF transmitter 123 b is present, for transmission to thenetwork. The digital baseband processor 129 may also provide controland/or feedback information to the RF receiver 123 a and to the RFtransmitter 123 b based on information from the processed signals. Thedigital baseband processor 129 may communicate information and/or datafrom the processed signals to the processor 125 and/or to the memory127. Moreover, the digital baseband processor 129 may receiveinformation from the processor 125 and/or to the memory 127, which maybe processed and transferred to the RF transmitter 123 b fortransmission to the network.

The RF transmitter 123 b may comprise suitable logic, circuitry, and/orcode that may enable processing of RF signals for transmission. The RFtransmitter 123 b may enable transmission of RF signals in a pluralityof frequency bands. Moreover, the RF transmitter 123 b may enabletransmitting signals in cellular frequency bands, for example. Eachfrequency band supported by the RF transmitter 123 b may have acorresponding front-end circuit for handling amplification and upconversion operations, for example. In this regard, the RF transmitter123 b may be referred to as a multi-band transmitter when it supportsmore than one frequency band. In another embodiment of the invention,the mobile terminal 120 may comprise more than one RF transmitter 123 b,wherein each of the RF transmitters 123 b may be a single-band or amulti-band transmitter.

The RF transmitter 123 b may quadrature up convert the basebandfrequency signal comprising I/Q components to an RF signal. The RFtransmitter 123 b may perform direct up conversion of the basebandfrequency signal to a baseband frequency signal, for example. In someinstances, the RF transmitter 123 b may enable digital-to-analogconversion of the baseband signal components received from the digitalbaseband processor 129 before up conversion. In other instances, the RFtransmitter 123 b may receive baseband signal components in analog form.

The processor 125 may comprise suitable logic, circuitry, and/or codethat may enable control and/or data processing operations for the mobileterminal 120. The processor 125 may be utilized to control at least aportion of the RF receiver 123 a, the RF transmitter 123 b, the digitalbaseband processor 129, and/or the memory 127. In this regard, theprocessor 125 may generate at least one signal for controllingoperations within the mobile terminal 120. The processor 125 may alsoenable executing of applications that may be utilized by the mobileterminal 120. For example, the processor 125 may execute applicationsthat may enable displaying and/or interacting with content received viaDVB-H transmission signals in the mobile terminal 120.

The memory 127 may comprise suitable logic, circuitry, and/or code thatmay enable storage of data and/or other information utilized by themobile terminal 120. For example, the memory 127 may be utilized forstoring processed data generated by the digital baseband processor 129and/or the processor 125. The memory 127 may also be utilized to storeinformation, such as configuration information, that may be utilized tocontrol the operation of at least one block in the mobile terminal 120.For example, the memory 127 may comprise information necessary toconfigure the RF receiver 123 a to enable receiving DVB-H transmissionin the appropriate frequency band.

FIG. 2B is a block diagram illustrating exemplary communication betweena multi-band RF receiver and a digital baseband processor in a mobileterminal, in accordance with an embodiment of the invention. Referringto FIG. 2B, there is shown a multi-band RF receiver 130, ananalog-to-digital converter (ADC) 134, and a digital baseband processor132. The multi-band RF receiver 130 may comprise a UHF front-end 131 a,an L-band front-end 131 b, a VHF front-end 131 c, a baseband block 133a, a received signal strength indicator (RSSI) block 133 b, and asynthesizer 133 c. The multi-band RF receiver 130, the analog-to-digitalconverter (ADC) 134, and/or the digital baseband processor 132 may bepart of a mobile terminal, such as the mobile terminal 120 in FIG. 2A,for example.

The multi-band RF receiver 130 may comprise suitable logic, circuitry,and/or code that may enable handling of VHF, UHF and L-band signals. Themulti-band RF receiver 130 may be enabled via an enable signal, such asthe signal RxEN 139 a, for example. In this regard, enabling themulti-band RF receiver 130 via the signal RxEN 139 a by a 1:10 ON/OFFratio may allow time slicing in DVB-H while reducing power consumption.At least a portion of the circuitry within the multi-band RF receiver130 may be controlled via the control interface 139 b. The controlinterface 139 b may receive information from, for example, a processor,such as the processor 125 in FIG. 2A, or from the digital basebandprocessor 132. The control interface 139 b may comprise more than onebit. For example, when implemented as a 2-bit interface, the controlinterface 139 a may be an inter-integrated circuit (12C) interface.

The VHF front-end 131 c may comprise suitable logic, circuitry, and/orcode that may enable low noise amplification and direct down conversionof VHF signals. In this regard, the VHF front-end 131 c may utilize anintegrated low noise amplifier (LNA) and mixers, such as passive mixers,for example. The VHF front-end 131 c may communicate the resultingbaseband frequency signals to the baseband block 133 a for furtherprocessing.

The UHF front-end 131 a may comprise suitable logic, circuitry, and/orcode that may enable low noise amplification and direct down conversionof UHF signals. In this regard, the UHF front-end 131 a may utilize anintegrated low noise amplifier (LNA) and mixers, such as passive mixers,for example. The UHF front-end 131 a may communicate the resultingbaseband frequency signals to the baseband block 133 a for furtherprocessing.

The L-band front-end 131 b may comprise suitable logic, circuitry,and/or code that may enable low noise amplification and direct downconversion of L-band signals. In this regard, the L-band front-end 131 bmay utilize an integrated LNA and mixers, such as passive mixers, forexample. The L-band front-end 131 b may communicate the resultingbaseband frequency signals to the baseband block 133 a for furtherprocessing. The multi-band RF receiver 130 may enable one of the VHFfront-end 131 c, the UHF front-end 131 a and the L-band front-end 131 bbased on current communication conditions.

The synthesizer 133 c may comprise suitable logic, circuitry, and/orcode that may enable generating the appropriate local oscillator (LO)signal for performing direct down conversion in either the VHF front-end131 c, the UHF front-end 131 a or the L-band front-end 131 b. Since thesynthesizer 133 c may enable fractional division of a source frequencywhen generating the LO signal, a large range of crystal oscillators maybe utilized as a frequency source for the synthesizer 133 c. Thisapproach may enable the use of an existing crystal oscillator in amobile terminal PCB, thus reducing the number of external componentsnecessary to support the operations of the multi-band RF receiver 130,for example. The synthesizer 133 c may generate a common LO signal forthe VHF front-end 131 c, the UHF front-end 131 a and for the L-bandfront-end 131 b. In this regard, the VHF front-end 131 c, the UHFfront-end 131 a and the L-band front-end 131 b may enable dividing theLO signal in order to generate the appropriate signal to perform downconversion from the VHF band, from the UHF band and from the L-bandrespectively. In some instances, the synthesizer 133 c may have at leastone integrated voltage controlled oscillator (VCO) for generating the LOsignal. In other instances, the VCO may be implemented outside thesynthesizer 133 c.

The baseband block 133 a may comprise suitable logic, circuitry, and/orcode that may enable processing of I/Q components generated from thedirect down conversion operations in the VHF front-end 131 c, the UHFfront-end 131 a and the L-band front-end 131 b. The baseband block 133 amay enable amplification and/or filtering of the I/Q components inanalog form. The baseband block 133 a may communicate the processed Icomponent, that is, signal 135 a, and the processed Q component, thatis, signal 135 c, to the ADC 134 for digital conversion.

The RSSI block 133 b may comprise suitable logic, circuitry, and/or codethat may enable measuring the strength, that is, the RSSI value, of areceived RF signal, whether VHF, UHF or L-band signal. The RSSImeasurement may be performed, for example, after the received RF signalis amplified in either the VHF front-end 131 c, the UHF front-end 131 aor the L-band front-end 131 b. The RSSI block 133 b may communicate theanalog RSSI measurement that is, signal 135 e, to the ADC 134 fordigital conversion.

The ADC 134 may comprise suitable logic, circuitry, and/or code that mayenable digital conversion of signals 135 a, 135 c, and/or 135 e tosignals 135 b, 135 d, and/or 135 f respectively. In some instances, theADC 134 may be integrated into the multi-band RF receiver 130 or intothe digital baseband processor 132.

The digital baseband processor 132 may comprise suitable logic,circuitry, and/or code that may enable processing and/or handling ofbaseband frequency signals. In this regard, the digital basebandprocessor 132 may be the same or substantially similar to the digitalbaseband processor 129 described in FIG. 2A. The digital basebandprocessor 132 may enable generating at least one signal, such as thesignals AGC_BB 137 a and AGC_RF 137 b, for adjusting the operations ofthe multi-band RF receiver 130. For example, the signal AGC_BB 137 a maybe utilized to adjust the gain provided by the baseband block 133 a onthe baseband frequency signals generated from either the VHF front-end131 c, the UHF front-end 131 a or the L-band front-end 131 b. In anotherexample, the signal AGC_RF 137 b may be utilized to adjust the gainprovided by an integrated LNA in either the VHF front-end 131 c, the UHFfront-end 131 a or the L-band front-end 131 b. In another example, thedigital baseband processor 132 may generate at least one control signalor control information communicated to the multi-band RF receiver 130via the control interface 139 b for adjusting operations within themulti-band RF receiver 130.

FIG. 2C is a block diagram illustrating an exemplary single-chipmulti-band RF receiver with an integrated LNA in each front-end, inaccordance with an embodiment of the invention. Referring to FIG. 2C,there is shown a single-chip multi-band RF receiver 140 a that maycomprise a VHF front-end 148 c, a UHF front-end 148 a, an L-bandfront-end 148 b, a baseband block 164, a digital frequency synthesizer188, a logarithmic amplifier (logarithmic amplifier) 172, a EAfractional-N synthesizer 174, a VCO block 176, a digital interface 160,an ADC 162, an oscillator 180, and a buffer 182.

The single-chip multi-band RF receiver 140 a may be fabricated using anyof a plurality of semiconductor manufacturing processes, for example,complimentary metal-oxide-semiconductor (CMOS) processes, bipolar CMOS(BiCMOS), or Silicon Germanium (SiGe). The single-chip multi-band RFreceiver 140 a may be implemented using differential structures tominimize noise effects and/or substrate coupling, for example. Thesingle-chip multi-band RF receiver 140 a may utilize low drop out (LDO)voltage regulators to regulate and clean up on-chip voltage supplies. Inthis regard, the LDO voltage regulators may be utilized to transformexternal voltage sources to the appropriate on-chip voltages.

When the single-chip multi-band RF receiver 140 a is implementedutilizing a CMOS process, some design considerations may includeachieving low noise figure (NF) values, wide-band operation, highsignal-to-noise ration (SNR), performing DC offset removal, achievinghigh input second-order and third-order intercept points (IIP2 andIIP3), and/or reducing I/Q mismatch, for example.

The single-chip multi-band RF receiver 140 a may receive UHF signals viaa first antenna 142 a, a UHF filter 144 a, and a first balum 146 a. TheUHF filter 144 a enables band pass filtering, wherein the band pass maybe about 470 to about 702 MHz for cellular signals, for example, orabout 470 to about 862 MHz, for other types of received signals, forexample. The balum 146 a enables balancing the filtered signals beforebeing communicated to the UHF front-end 148 a.

The single-chip multi-band RF receiver 140 a may receive L-band signalsvia a second antenna 142 b, an L-band filter 144 b, and a second balum146 b. The L-band filter 144 b enables band pass filtering, wherein theband pass may be about 1670 to about 1675 MHz for signals in US systems,for example, or about 1450 to about 1490 MHz, for signals in Europeansystems, for example. The balum 146 b enables balancing the filteredsignals before being communicated to the L-band front-end 148 a. In someinstances, antennas 142 a and 142 b may be implemented utilizing asingle antenna communicatively coupled to the single-chip multi-band RFreceiver 140 a that may support receiving radio signals operating in theUHF IV/V and/or L-band, for example.

The single-chip multi-band RF receiver 140 a may receive VHF signals viaa third antenna 142 c, a VHF filter 144 c, and a third balum 146 c. TheVHF filter 144 c enables band pass filtering, wherein the band pass maybe about 174 to about 240 MHz, for example. The balum 146 c enablesbalancing the filtered signals before being communicated to the VHFfront-end 148 c.

The UHF front-end 148 a may comprise a variable low noise amplifier(LNA) 150 a, a mixer 152 a, a mixer 154 a, and a LO signal divider 156.The variable LNA 150 a may comprise suitable logic and/or circuitry thatmay enable amplification of the UHF signals received. Matching betweenthe output of the balum 146 a and the input of the variable LNA 150 amay be achieved by utilizing off-chip series inductors, for example. Thevariable LNA 150 a may implement continuous gain control by currentsteering that may be controlled by a replica scheme within the variableLNA 150 a. The gain of the variable LNA 150 a may be adjusted via thesignal AGC_RF 137 b, for example.

The mixers 152 a and 154 a may comprise suitable logic and/or circuitrythat may enable generating in-phase (I) and quadrature (Q) components ofthe baseband frequency signal based on direct down conversion of theamplified received UHF signal with the quadrature signals 186I and 186Qgenerated by the divider block 156. The mixers 152 a and 154 a may bepassive mixers in order to achieve high linearity and/or low flickernoise, for example. The LO signal divider 156 may comprise suitablelogic, circuitry, and/or code that may enable dividing of the LO signal186 by a factor of 2 (:/2) or a factor of 3 (:/3) and at the same timeprovide quadrature outputs 186I and 186Q, wherein 186I and 186Q have 90degrees separation between them. The factor of 3 division may be usedwhen the received UHF signal band is about 470 to about 600 MHz, forexample. The factor of 2 division may be used when the received UHFsignal band is about 600 to about 900 MHz, for example. The I/Qcomponents generated by the mixers 152 a and 154 a may be communicatedto the baseband block 164.

The L-band front-end 148 b may comprise a variable LNA 150 b, a mixer152 a, a mixer 154 a, and a LO signal generator 158. The variable LNA150 a may comprise suitable logic and/or circuitry that may enableamplification of the L-band signals received. Matching between theoutput of the balum 146 b and the input of the variable LNA 150 b may beachieved by utilizing off-chip series inductors, for example. Thevariable LNA 150 b may implement continuous gain control by currentsteering that may be controlled by a replica scheme within the variableLNA 150 b. The gain of the variable LNA 150 b may be adjusted via thesignal AGC_RF 137 b, for example.

The mixers 152 b and 154 b may comprise suitable logic and/or circuitrythat may enable generating I/Q components of the baseband frequencysignal based on the direct down conversion of the amplified receivedL-band signal with the LO signals 158I and 158Q generated by the LOgenerator block 158. The mixers 152 b and 154 b may be passive mixers inorder to achieve high linearity and/or low flicker noise, for example.The LO signal generator 158 may comprise suitable logic, circuitry,and/or code that may enable generation of quadrature LO signals 158I and158Q, that is, signals with 90 degree phase split between them, from theLO signal 186. The I/O components generated by the mixers 152 b and 154b may be communicated to the baseband block 164.

The VHF front-end 148 c may comprise a variable low noise amplifier(LNA) 150 c, a mixer 152 c, a mixer 154 c, and a LO signal divider 157.The variable LNA 150 c may comprise suitable logic and/or circuitry thatmay enable amplification of the VHF signals received. Matching betweenthe output of the balum 146 c and the input of the variable LNA 150 cmay be achieved by utilizing off-chip series inductors, for example. Thevariable LNA 150 c may implement continuous gain control by currentsteering that may be controlled by a replica scheme within the variableLNA 150 c. The gain of the variable LNA 150 c may be adjusted via thesignal AGC_RF 137 b, for example.

The mixers 152 c and 154 c may comprise suitable logic and/or circuitrythat may enable generating in-phase (I) and quadrature (Q) components ofthe baseband frequency signal based on direct down conversion of theamplified received VHF signal with the quadrature signals 187I and 187Qgenerated by the divider block 157. The mixers 152 c and 154 c may bepassive mixers in order to achieve high linearity and/or low flickernoise, for example. The LO signal divider 157 may comprise suitablelogic, circuitry, and/or code that may enable dividing of the LO signal187 by a factor of 6 (:/6) or a factor of 8 (:/8) and at the same timeprovide quadrature outputs 187I and 187Q, wherein 187I and 187Q have 90degrees separation between them. The I/Q components generated by themixers 152 c and 154 c may be communicated to the baseband block 164.

The digital frequency synthesizer 188 may comprise suitable logic,circuitry, and/or code that may enable generation of a reference signalbased on a clock timing signal, and on a control input signal. Invarious embodiments of the invention, the digital frequency synthesizer188 may implement a look up table (LUT) function wherein a given clocktiming signal and control input signal combination may correspond to afrequency, phase, and/or magnitude for a generated reference signal.Data utilized for the LUT function may be stored and/or retrieved fromthe memory 127 (FIG. 2A), for example. In other embodiments of theinvention, the digital frequency synthesizer 188 may comprise anover-sampling digital to analog conversion (DAC) function in which thedigital frequency synthesizer 188 performs digital sampling of the clocktiming signal. A rate of digital sampling may be determined based on thecontrol input signal.

The logarithmic amplifier 172 may comprise suitable logic, circuitry,and/or code that may enable generation of a wideband, received signalstrength indicator (RSSI) signal, such as the signal 135 e, based on theoutput of the variable LNA 150 a. The RSSI signal indicates the totalamount of signal power that is present at the output of the LNA, forexample. The RSSI signal may be utilized by, for example, the digitalbaseband processor 132 in FIG. 2C, to adjust the gain of the variableLNA 150 a in the presence of RF interference to achieve NF and/orlinearity performance that meets blocking and/or intermodulationspecifications, for example. In this regard, interference may refer toblocker signals, for example. Blocker signals may be unwanted signals infrequency channels outside the wanted or desired channel that maydisturb the reception of the wanted signals. This effect may be a resultof blockers generating large signals within the receiver path. Theselarge signals may introduce harmonics, intermodulation products, and/orunwanted mixing products that crosstalk with the wanted signals. Inanother embodiment of the invention, the logarithmic amplifier 172 mayenable generating a wideband, RSSI signal, such as the signal 135 e,based on the output of the variable LNA 150 b. In this instance, theRSSI signal may be utilized by to adjust the gain of the variable LNA150 b.

The baseband block 164 may comprise an in-phase component processingpath and a quadrature component processing path. The in-phase processingpath may comprise at least one programmable gain amplifier (PGA) 166 a,a baseband filter 168 a, and at least one PGA 170 a. The quadraturecomponent processing path may comprise at least one PGA 166 b, abaseband filter 168 b, and at least one PGA 170 b. The PGAs 166 a, 166b, 170 a, and 170 b may comprise suitable logic, circuitry, and/or codethat may enable amplification of the down converted components of thebaseband frequency signal generated by the RF front-end. The gain of thePGAs 166 a, 166 b, 170 a, and 170 b may be digitally programmable. Inaddition, at the output of the PGAs 166 a and 166 b, a programmable polemay be utilized to reduce linearity requirements for the basebandfilters 168 a and 168 b respectively. Since the static and time-varyingDC offset may saturate the operation of the single-chip multi-band RFreceiver 140 a, the PGAs 166 a, 166 b, 170 a, and 170 b may utilize DCservo loops to address DC offset issues. The gain of the PGAs 166 a, 166b, 170 a, and/or 170 b may be controlled via the AGC_BB signal 137 a,for example. In this regard, the ADC 162 may be utilized to providedigital control of the PGAs 166 a, 166 b, 170 a, and/or 170 b when theAGC_BB signal 137 a is an analog signal.

The baseband filters 168 a and 168 b may comprise suitable logic,circuitry, and/or code that may enable channel selection, for example.Channel selection may be performed by filters, such as an N^(th) orderlowpass Chebyschev filter implemented by opamp-RC active integrators ina leapfrog configuration, for example. For the correct tuning of thecharacteristics of the filters, an on-chip auto-calibration loop may beactivated upon power-up. The auto-calibration loop may set up thecut-off frequency, f_(−3dB) to the correct vale required to meet therequirements of the communications standard for which the receiver isdesigned. For example, in DVB-T/DVB-H, the value f_(−3dB) of the filtercut-off frequency may be set to a value from 2 to 5 MHz thus supportingthe different channel bandwidths of 5-8 MHz specified by DVB-T/DVB-Hstandards. During auto-calibration, a tone at the appropriate f_(−3dB)may be generated by the digital frequency synthesizer 188 and may beapplied at the input of the baseband filters 168 a and 168 b forcomparison with the filter output of a root-mean-squared (RMS) detector.A digitally controlled loop may be utilized to adjust the basebandfilter bandwidth until the output of the baseband filter and the RMSdetector are the same.

The Σ−Δ fractional-N synthesizer 174 may comprise suitable logic,circuitry, and/or code that may enable LO generation that may beindependent of the reference crystal frequency, such as the crystal 178,for example. In this regard, the synthesizer 174 may generate a signal,such as the signal 190, for example, to control the operation of the VCOblock 176 and therefore the generation of the LO signal 186. Since thesynthesizer 174 may enable fractional synthesis, the single-chip multiband RF receiver 140 a may utilize the same crystal utilized by otheroperations in the mobile terminal while maintaining fine tuningcapability. The synthesizer 174 may receive a reference frequency signalfrom the crystal 178 via an oscillator 180, for example. The output ofthe oscillator 180 may also be buffered by the buffer 182 to generate aclock signal 184, for example.

The VCO block 176 may comprise suitable logic, circuitry, and/or codethat may enable generating the LO signal 186 utilized by the VHFfront-end 148 c, the UHF front-end 148 a and the L-band front-end 148 bfor direct down conversion of the received RF signals. The VCO block 176may comprise at least one VCO, wherein each VCO may have cross-coupledNMOS and PMOS devices and metal-oxide-semiconductor (MOS) varactors inan accumulation mode for tuning. In this regard, a switched varactorbank may be utilized for providing coarse tuning. The VCO block 176 mayprovide a range of about 1.2 to about 1.8 GHz when implemented utilizingtwo VCOs, for example. When more than one VCO is utilized inimplementing the VCO block 176, selecting the proper VCO for generatingthe LO signal 186 may be based on the type of RF signal being receivedby the single-chip multi band RF receiver 140 a.

The digital interface 160 may comprise suitable logic, circuitry, and/orcode that may enable controlling circuitry within the single-chip multiband RF receiver 140 a. The digital interface 160 may comprise aplurality of registers for storing control and/or operationalinformation for use by the single-chip multi-band RF receiver 140 a. Thedigital interface 160 may enable receiving the signal RxEN 139 a thatmay be utilized to perform 1:10 ON/OFF ratio time slicing in DVB-H whilereducing power consumption. Moreover, the digital interface 160 mayenable receiving the control interface 139 b from, for example, aprocessor, such as the processor 125 in FIG. 2A, or from the digitalbaseband processor 132 in FIG. 2C. The control interface 139 b maycomprise more than one bit. The control interface 139 b may be utilizedto control the synthesis operations of the synthesizer 174 and/or thefiltering operations of the baseband filters 168 a and 168 b. Thecontrol interface 139 b may also be utilized to adjust the bias ofcircuits within the single-chip multi-band RF receiver 140 a, such asthose of the variable LNAs 150 a and 150 b, the PGAs 166 a, 166 b, 170a, and 170 b, and/or the baseband filters 168 a and 168 b, for example.

FIG. 2D is a diagram for an exemplary direct filter calibration schemeutilizing filtering, which may be utilized in connection with anembodiment of the invention. Referring to FIG. 2D, there is shown acrystal oscillator 206, a frequency divider block 208, a filtering block222, a filter block 224, and a control block 226. The crystal oscillatorblock 206 may substantially comprise the functions of the crystal 178,and the oscillator 180 (FIG. 2C). The frequency divider block 208 may besubstantially as described in FIG. 1. The control block 226 may besubstantially as described for the control block 212 in FIG. 1. Thefilter block 224 may substantially comprise the functions of thebaseband filter 168 a. When the value for the f_(−3dB) filter cut-offfrequency is based on the values of R and C components, the filter 224may comprise an opamp-RC filter circuit. For the opamp-RC filtercircuit, the f_(−3dB) filter cut-off frequency may be referred to as af_(−3dB) (RC) filter cut-off frequency. When the value for the f_(−3dB)filter cut-off frequency is based on the values of transconductors and Ccomponents, the filter 224 may comprise a G_(m)C filter circuit. For theRC filter circuit, the f_(−3dB) filter cut-off frequency may be referredto as a f_(—)3 dB (G_(m)C) filter cut-off frequency.

The filtering block 222 may comprise suitable logic, circuitry, and/orcode that may enable generation of an output signal by removing harmonicfrequency components from a received input signal. The function of thefiltering block 222 may be practiced by implementations comprising a lowpass filter, a high pass filter, and/or a band pass filter.

In operation, the crystal oscillator 206 may enable generation of acrystal (xtal) timing signal. The crystal timing signal may becharacterized by a crystal frequency, f_(Xtal). The frequency divider208 may receive the crystal timing signal as an input signal. Thefrequency divider 208 may utilize a frequency division factor, f_(D), togenerate a reference timing signal characterized by a referencefrequency, f_(Ref). The value of the reference frequency may beapproximately equal to the ratio of the value of the reference frequencyand the value of the frequency division factor, f_(Ref)/f_(D).

The filtering block 222 may enable generation of a filtered referencetiming signal based on the reference timing signal. The filteredreference timing signal may also be characterized by the referencefrequency. The filtering block 222 may generate the filtered referencetiming signal may attenuating frequency components in the referencetiming signal, which are characterized by harmonic frequencies of thereference frequency.

For a filter block 224 comprising an opamp-RC filter circuit, thecontrol signal, f_(Control), generated by the control block 226 maycause the filter block 224 to adjust the R and/or C values for the Rand/or C components. As a result of the adjustment, the correspondingvalue for the f_(−3dB) (RC) filter cut-off frequency may be adjusted.The filter block 224 may generate a filter calibration signal byfiltering the filtered reference timing signal. The filter block 224 mayperform the filtering function by attenuating certain frequencycomponents in the filtered reference timing signal based on the f_(−3dB)(RC) filter cut-off frequency. The filtering function performed by thefilter block 224 may modify an amplitude parameter and/or phaseparameter, which characterizes at least a portion of the frequencycomponents contained within the filtered reference timing signal.

For a filter block 224 comprising an G_(m)C filter circuit, the controlsignal, f_(Control), generated by the control block 226 may cause thefilter block 224 to adjust the G_(m) and/or C values for thetransconductor and/or C components. As a result of the adjustment, thecorresponding value for the f_(−3dB) (G_(m)C) filter cut-off frequencymay be adjusted. The filter block 224 may generate a filter calibrationsignal by filtering the filtered reference timing signal. The filterblock 224 may perform the filtering function by attenuating frequencycomponents in the filtered reference timing signal based on the f_(−3dB)(G_(m)C) filter cut-off frequency. The filtering function performed bythe filter block 224 may modify an amplitude parameter and/or phaseparameter, which characterizes at least a portion of the frequencycomponents contained within the filtered reference timing signal.

The control block 226 may compare values of the amplitude parametersand/or phase parameters, which characterize the corresponding frequencycomponents in the filter calibration signal received from the filterblock 224. The values of the amplitude parameters and/or phaseparameters may be compared with expected values for the amplitude and/orphase parameters for the corresponding frequency components. The controlblock may generate a control signal, f_(Control), based on thecomparison.

The component value mismatch problem may be avoided in comparison to thesystem illustrated in FIG. 1 since the control signal, f_(Control), isgenerated based on the filter calibration signal generated by the filterblock 224. This calibration method is direct as opposed to the indirectmethod in FIG. 1. As with the system illustrated in FIG. 1, adisadvantage in this method is that that the accuracy of the calibrationmay also be limited based on the range of values for frequency, f_(Ref),and/or phase, φ_(Ref), which may be generated by the frequency dividerblock 208. In addition, embodiments of the system illustrated in FIG. 2Dmay require additional circuitry to implement the filtering block 222.

FIG. 3A is a block diagram of an exemplary analog baseband processingsystem supporting auto-calibration, in accordance with an embodiment ofthe invention. Referring to FIG. 3A, the baseband processing block 300 amay comprise a plurality of programmable gain amplifiers (PGAs) 304 a,308 a, 310 a, and 314 a, and baseband filters 306 a and 312 a.

For example, the baseband processing block 300 a may comprise anin-phase (I) component processing path comprising PGAs 304 a and 308 a,and a baseband filter 306 a. The in-phase component processing path ofthe baseband processing block 300 a may process an input in-phase (I)signal 316 a to generate an output in-phase signal 318 a. The inputin-phase signal 316 a may comprise a down converted component of abaseband frequency signal generated by an RF front end, for example. Thebaseband processing block 300 a may also comprise a quadrature component(Q) processing path comprising PGAs 310 a and 314 a, and a basebandfilter 312 a. The quadrature component processing path of the basebandprocessing block 300 a may process an input quadrature (Q) signal 320 ato generate an output quadrature signal 322 a. The input quadraturesignal 320 a may comprise a down converted component of a basebandfrequency signal generated by an RF front end, for example.

The PGAs 304 a, 308 a, 310 a, and 314 a may comprise suitable logic,circuitry, and/or code that may enable amplification of the downconverted components of the baseband frequency signals 316 a and 320 a.The PGAs 304 a, 308 a, 310 a, and 314 a may be digitally programmable.For example, at the output of the PGAs 304 a and 310 a, a programmablepole may be utilized to reduce linearity requirements for the basebandfilters 306 a and 312 a, respectively. Furthermore, the PGAs 304 a, 308a, 310 a, and 314 a may utilize DC servo loops to address DC offsetissues. The baseband filters 306 a and 312 a may comprise suitablelogic, circuitry, gain and/or code that may enable channel selection,for example. Channel selection may be performed by a filter bank, suchas an Nth order Chebyschev filter implemented by active integrators, forexample.

FIG. 3B is a schematic diagram of an exemplary opamp-RC baseband filterthat may be used in accordance with an embodiment of the invention.Referring to FIG. 3B, the baseband filter 300 b may comprise a sixthorder Chebyschev filter, for example. The Chebyschev filter 300 b maycomprise a plurality of operational amplifiers (opamps) a1, . . . , a6,a plurality of variable capacitors c1, . . . , c6, and a plurality ofresistors r1, . . . , r14. In one embodiment of the invention, theopamp-RC integrators a1-c1-r1 and a6-c6-r8 may be arranged in a leapfrogformation. Each of the capacitors c1, . . . , c6 may be implemented as abinary weighted array of capacitors that may be controlled by 6 bits,for example.

In operation, the cut-off frequency f_(−3dB) of the Chebyschev filter300 b may be changed during channel selection. For example, the cut-offfrequency f_(−3dB) of the Chebyschev filter 300 b may be set to a valuefrom 2 MHz, for example, thereby supporting channel bandwidth of about 5MHz to about 8 MHz, which is specified by the DVB-T standard. Eventhough the baseband filter 300 b comprises a sixth order Chebyschevfilter, the present invention may not be so limited and an Nth orderlow-pass filter (LPF) may be utilized instead.

Even though the baseband filter 300 b is described as a Chebyschevfilter, the present invention may not be so limited. Other types offilters may also be utilized, such as Butterworth, Elliptic etc., forexample. Furthermore, even though operational amplifier RC integratorsare utilized within the filter 300 b, the present invention may not beso limited and other integrator implementations may also be utilized,such as a Gm-C integrator. Additionally, topologies other than theleapfrog formation may be utilized, such as cascaded biquads.

FIG. 3C is a block diagram of an exemplary baseband processing systemusing opamp-RC filters and an auto-calibration loop, in accordance withan embodiment of the invention. Referring to FIG. 3C, the basebandprocessing block 300 c may comprise a plurality of programmable gainamplifiers (PGAs) 302 c, 304 c, 318 c, and 320 c, and baseband filters310 c and 312 c. In addition, the baseband processing block may comprisean auto-calibration loop circuitry. The auto-calibration loop circuitrymay comprise switches 306 c, 314 c, 308 c, and 316 c, a digitalfrequency synthesizer 188, a fractional-N synthesizer 174, a crystal178, an oscillator 180, an amplifier 324 c, root-means-square (rms)blocks 326 c and 328 c, a comparator 330 c, and control logic block 334c. The digital frequency synthesizer 188, Σ−Δ fractional-N synthesizer174, crystal 178, and oscillator 180 may be substantially as describedin FIG. 2C.

Even though rms blocks are used within the baseband processing block 300c, the present invention may not be so limited and peak detectors may beused instead of the rms blocks.

The functionality of the PGAs 302 c, 318 c, 304 c, and 320 c may besimilar to the functionality of the PGAs 304 a, 308 a, 310 a, and 314 ain FIG. 3A, respectively. Similarly, the functionality of the basebandfilters 310 c and 312 c may be the same as the functionality of thebaseband filters 306 a and 312 a in FIG. 3A, respectively. For example,the baseband filters 310 c and 312 c may each comprise a sixth orderChebyschev filters, such as the Chebyschev filter 311 c or theChebyschev filter 300 b in FIG. 3B.

During an exemplary auto-calibration of the quadrature-phase signalpath, the switch 308 c may communicatively couple the output from thedigital frequency synthesizer 188 to the input for the baseband filter312 c. The switch 316 c may communicatively couple the output from thebaseband filter 312 c to the input for the rms block 326 c. The digitalfrequency synthesizer 188 may generate a reference frequency signal f−3dB. The reference frequency signal may then be applied at the input ofthe baseband filter 312 c and the amplifier 324 c. The amplifier 324 cmay attenuate the reference frequency signal by 3 dB, for example. Theattenuated frequency signal may then be communicated to the rms block328 c. After the baseband filter 312 c filters the reference frequencysignal communicated from the digital frequency synthesizer 188, thefiltered reference frequency signal may be communicated to the rms block326 c. A corresponding exemplary auto-calibration may be performed forthe in-phase signal path

Even though the digital frequency synthesizer 188 generates a referencefrequency signal f_(−3dB) that corresponds to the frequency where thefilter attenuates by 3 dB the present invention may not be so limited.In this regard, digital frequency synthesizer 188 may generate areference frequency signal f_(−x dB) that corresponds to the frequencyof a main signal attenuated from the filter by x dB in accordance withthe expected frequency response of the baseband filters 310 c and 312 c.In such instances, the amplifier 324 c may correspondingly attenuate thesignal generated by the digital frequency synthesizer 188.

While the digital frequency synthesizer 188 may receive an input signalfrom the Σ−Δ fractional-N synthesizer 174 in the exemplary system ofFIG. 3C, various embodiments of the invention may not be so limited. Invarious embodiments of the invention, the digital frequency synthesizer188 may receive an LO signal from the phase locked loop (PLL) present ina communication receiver. In one aspect of the invention, a scheme forcalibrating a filter in a communication receiver without requiringadditional circuitry may be provided. In various embodiments of theinvention, the Σ−Δ fractional-N synthesizer 174 may be utilized toenable the generation of a wide range of reference signal frequencies.In addition, the Σ−Δ fractional-N synthesizer 174 may enable moreaccurate generation of a specified frequency f_(−3dB) than may be thecase with many conventional filter calibration schemes. In anotherembodiment of the invention, a digital frequency synthesizer 188 mayprovide even greater accuracy in the generation of a specific frequencyf_(−3dB).

The rms blocks 326 c and 328 c may perform an averaging function, forexample, on the filtered reference frequency signal and the attenuatedreference frequency signal, respectively. The averaged filteredreference frequency signal and the attenuated reference frequency signalmay be compared by the comparator 330 c. A comparator output signal maybe communicated from the comparator 330 c to the control logic block 334c. The control logic block 334 c may comprise suitable circuitry, logic,and/or code and may enable generation of a filter control signal 336 cand/or synthesizer control signal 338 c. The control logic block 334 cmay use a clock signal 332 c during control signal generation. In oneexemplary embodiment of the invention, if a sixth order Chebyschevfilter is used within the baseband processing block 300 c, the filtercontrol signal 336 c may comprise a 6-bit signal. In this regard, sixbits may be used to program or adjust the capacitance of each variablecapacitor c1, . . . , c6 in the filter 311 c.

The filter control signal 336 c may be communicated to each of thebaseband filters 310 c, 312 c. The baseband filters 310 c and 312 c mayadjust capacitance of the variable capacitors within the filters and,thereby, change the cut-off frequency that determines filter bandwidth.The cut-off frequency and filter bandwidth of the filters 310 c and 312c may be adjusted until attenuation of the reference frequency signal bythe filter 312 c equals 3 dB, for example. The synthesizer controlsignal 338 c may be communicated to the digital frequency synthesizerfrom the control logic block 334 c. The synthesizer control signal 338 cmay be utilized by the digital frequency synthesizer 188 to generate areference frequency signal based on a received LO signal.

Even though an auto-calibration loop is described with respect to thequadrature signal path of the baseband processing block 300 c, the sameauto-calibration loop circuitry, such as the digital frequencysynthesizer 188, amplifier 324 c, rms blocks 326 c and 328 c, comparator330 c and control logic block 334 c, may be used with regard to thein-phase signal path of the baseband processing block 300 c.

In one embodiment of the invention, for DVB-T applications, for example,an on-chip auto-calibration loop may be activated within the basebandprocessing block 300 c upon power-up. The auto-calibration loop mayadjust the cut-off frequency f_(−3dB) of the filter response of basebandfilters 310 c and 312 c to a value from about 2 MHz to about 5 MHz, forexample. In this regard, the baseband processing block 300 c may supporta plurality of channel bandwidths of 4-10 MHz, such as bandwidthsspecified by the DVB-T standard. A similar principle may apply to aplurality of channel bandwidths required by a specific communicationstandard. The auto-calibration loop may be utilized to enable adjustmentof the filter cut-off frequency to a selected value as required, giventhat proper component value ranges have been provided in the design ofthe system. For example, the filter cut-off frequency may be adjusted to210 kHz as required by the ISDB-T standard.

FIG. 4 is a flow diagram illustrating exemplary steps in a filtercalibration scheme using fractional-N frequency synthesized signals, inaccordance with an embodiment of the invention. Referring to FIG. 4, instep 402 a reference frequency at which to characterize a basebandfilter 312 c may be determined. The reference frequency may correspondto an expected L_(−3dB) cutoff frequency for the baseband filter 312 c.In step 404, a local oscillator (LO) signal and synthesizer controlsignal 338 c may be generated. In various embodiments of the invention,the LO signal may be generated by a Σ−Δ fractional-N synthesizer 174,and the synthesizer control signal 338 c may be generated by the controllogic block 334 c.

In step 406, a reference signal may be generated. The reference signalmay be characterized by the reference frequency, L_(−3dB). In variousembodiments of the invention, the reference signal may be generated bythe digital frequency synthesizer 188. The digital frequency synthesizer188 may generate the reference signal based on the LO signal and thesynthesizer control signal 338 c.

In step 408, a filtered version of the reference frequency signal and anattenuated version of the reference frequency signal may be generated.In various embodiments of the invention, the filtered version of thereference frequency signal may be generated by applying the filteringcharacteristics of the baseband filter 312 c to the reference frequencysignal, while the attenuated version of the reference frequency signalmay be generated based on the reference frequency signal by theamplifier 324 c.

In step 410, the filtered version of the reference frequency signal andthe attenuated version of the reference frequency signal may be comparedby the comparator 330 c. The comparison may be based on an amplitudeand/or phase of the filtered version of the reference frequency signalversus the corresponding amplitude and/or phase of the attenuatedversion of the reference frequency signal. Prior to comparing, therespective signals may be averaged.

In step 412, a filter control signal 336 c may be generated and/ormodified based on the comparison from step 410. In various embodimentsof the invention, the filter control signal may be generated and/ormodified by the control logic block 334 c.

In step 414, a resistance, transconductance, and/or capacitance valuemay be modified for a baseband filter 312 c based on the filter controlsignal 336 c generated and/or modified in step 412. In variousembodiments of the invention that comprise an RC filter, a resistanceand/or capacitance value may be modified based on the filter controlsignal 336 c. In various embodiments of the invention that comprise aG_(m)C filter, a transconductance and/or capacitance value may bemodified based on the filter control signal 336 c.

Aspects of a system for filter calibration using fractional-Nsynthesized signals may include a single-chip multi-band RF receiver 140a that enables generation of a LO signal by a PLL circuit within thesingle-chip, and enables calibration of a frequency response for afilter circuit integrated within the chip. The frequency response mayinclude a filter cut-off frequency and/or a filter phase shift. Thefilter cut-off frequency may represent a frequency beyond which thefilter circuit may attenuate signal amplitudes by at least 3 dB, forexample. The filter phase shift may represent a phase shift induced insignals that are processed by the filter circuit. A reference signal maybe generated based on the generated LO signal and a synthesizer controlsignal. The frequency response may be calibrated by adjusting the filtercircuit based on the generated reference signal. For an RC filter,exemplary parameters may comprise resistance values and/or capacitancevalues. For a G_(m)C filter, exemplary parameters may comprisetransconductance values and/or capacitance values. In variousembodiments of the invention, the function of the PLL may be implementedby a Σ−Δ fractional-N synthesizer 174. The function of the filtercircuit may be implemented by a baseband filter 312 c.

The single-chip multi-band RF receiver 140 a may enable generation of areference signal based on the generated LO signal and on a synthesizercontrol signal. The reference signal may be generated by the digitalfrequency synthesizer 188. The synthesizer control signal may begenerated by a control logic block 334 c. The single-chip multi-band RFreceiver 140 a may also enable generation of an attenuated referencesignal by attenuating the reference signal. The reference signal may beattenuated by the amplifier 324 c. The single-chip multi-band RFreceiver 140 a may enable generation of a filtered reference signalbased on filtering of the reference signal by the filter circuit. Thesingle-chip multi-band RF receiver 140 a may enable comparison of theattenuated reference signal and the filtered reference signal. Thecomparison may be performed by the comparator 330 c.

The single-chip multi-band RF receiver 140 a may also enable computationof averages for the attenuated reference signal and for the filteredreference signal, prior to performing the comparison. Each average maybe computed by an rms block 326 c. The single-chip multi-band RFreceiver 140 a may enable generation of one or more filter controlsignals based on the comparison. The control logic block 334 c mayenable generation of the filter control signals 336 c.

The single-chip multi-band RF receiver 140 a may enable adjustment of aresistance value, and/or a capacitance value, for the filter circuitintegrated within the single chip based on the generated one or morecontrol signals. The single-chip multi-band RF receiver 140 a may enablemodification of a cut-off frequency for the filter circuit integratedwithin the chip based on the adjusting of the resistance value, and/orthe capacitance value.

The single-chip multi-band RF receiver 140 a may enable adjustment of atransconductance value, and/or a capacitance value, for the filtercircuit integrated within the chip based on the generated one or morecontrol signals. The single-chip multi-band RF receiver 140 a may enablemodification of a cut-off frequency for the filter circuit integratedwithin the chip based on the adjusting of the transconductance value,and/or the capacitance value.

The filter circuit integrated within the single-chip multi-band RFreceiver 140 a may comprise a low-pass filter. An exemplary low passfilter may comprise a Chebychev filter.

Accordingly, aspects of the invention may be realized in hardware,software, firmware and/or a combination thereof. The invention may berealized in a centralized fashion in at least one computer system or ina distributed fashion where different elements are spread across severalinterconnected computer systems. Any kind of computer system or otherapparatus adapted for carrying out the methods described herein issuited. A typical combination of hardware, software and firmware may bea general-purpose computer system with a computer program that, whenbeing loaded and executed, controls the computer system such that itcarries out the methods described herein.

One embodiment of the present invention may be implemented as a boardlevel product, as a single chip, application specific integrated circuit(ASIC), or with varying levels integrated on a single chip with otherportions of the system as separate components. The degree of integrationof the system will primarily be determined by speed and costconsiderations. Because of the sophisticated nature of modernprocessors, it is possible to utilize a commercially availableprocessor, which may be implemented external to an ASIC implementationof the present system. Alternatively, if the processor is available asan ASIC core or logic block, then the commercially available processormay be implemented as part of an ASIC device with various functionsimplemented as firmware.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the present inventionwill include all embodiments falling within the scope of the appendedclaims.

1-24. (canceled)
 25. A method for processing information in a wirelesscommunication system, the method comprising: generating a test signalwithin a single-chip multi-band RF receiver; generating a filter controlsignal within said single-chip multi-band RF receiver; and calibrating afrequency response for a filter circuit integrated within saidsingle-chip multi-band RF receiver, by adjusting said filter circuitbased on one or both of said test signal and said filter control signal.26. The method according to claim 25, comprising generating, within saidsingle-chip multi-band RF receiver, an attenuated test signal byattenuating said test signal.
 27. The method according to claim 25,comprising generating, within said single-chip multi-band RF receiver, afiltered test signal based on filtering of said test signal by saidfilter circuit.
 28. The method according to claim 27, comprisingcomparing, within said single-chip multi-band RF receiver, an attenuatedtest signal and said filtered test signal.
 29. The method according toclaim 28, comprising computing, within said single-chip multi-band RFreceiver, an average for one or both of said attenuated test signal andsaid filtered test signal, prior to said comparing.
 30. The methodaccording to claim 28, comprising generating said filter control signalbased on said comparing.
 31. The method according to claim 30,comprising adjusting, within said single-chip multi-band RF receiver,one or both of a resistance value, and a capacitance value, for saidfilter circuit integrated within said single-chip multi-band RFreceiver, based on said generated filter control signal.
 32. The methodaccording to claim 31, comprising modifying a cut-off frequency for saidfilter circuit integrated within said single-chip multi-band RF receiverbased on said adjusting one or both of said resistance value, and saidcapacitance value.
 33. The method according to claim 30, comprisingadjusting one or both of a transconductance value, and a capacitancevalue, for said filter circuit integrated within said single-chipmulti-band RF receiver based on said generated filter control signal.34. The method according to claim 33, comprising modifying a cut-offfrequency for said filter circuit integrated within said single-chipmulti-band RF receiver based on said adjusting one of both of saidtransconductance value, and said capacitance value.
 35. The methodaccording to claim 25, wherein said filter circuit integrated withinsaid single-chip multi-band RF receiver comprises a low-pass filter. 36.The method according to claim 35, wherein said low-pass filter comprisesa Chebyschev filter.
 37. A system for processing information in awireless communication system, the system comprising: one or morecircuits that enable generation of a test signal within a single-chipmulti-band RF receiver; said one or more circuits enable generation of afilter control signal within said single-chip multi-band RF receiver;and said one or more circuits enable calibration of a frequency responsefor a filter circuit integrated within said single-chip multi-band RFreceiver, by adjusting said filter circuit based on one or both of saidtest signal and said filter control signal.
 38. The system according toclaim 37, wherein said one or more circuits enable generation, withinsaid single-chip multi-band RF receiver, of an attenuated test signal byattenuating said test signal.
 39. The system according to claim 37,wherein said one or more circuits enable generation, within saidsingle-chip multi-band RF receiver, of a filtered test signal based onfiltering of said test signal by said filter circuit.
 40. The systemaccording to claim 39, wherein said one or more circuits enablecomparing, within said single-chip multi-band RF receiver, of anattenuated test signal and said filtered test signal.
 41. The systemaccording to claim 40, wherein said one or more circuits enablecomputation, within said single-chip multi-band RF receiver, of anaverage for one or both of said attenuated test signal and said filteredtest signal, prior to said comparing.
 42. The system according to claim40, wherein said one or more circuits enable generation of said filtercontrol signal based on said comparing.
 43. The system according toclaim 42, wherein said one or more circuits enable adjustment, withinsaid single-chip multi-band RF receiver, of one or both of a resistancevalue, and a capacitance value, for said filter circuit integratedwithin said single-chip multi-band RF receiver, based on said generatedfilter control signal.
 44. The system according to claim 43, whereinsaid one or more circuits enable modification of a cut-off frequency forsaid filter circuit integrated within said single-chip multi-band RFreceiver based on said adjusting one or both of said resistance value,and said capacitance value.
 45. The system according to claim 42,wherein said one or more circuits enable adjustment of one or both of atransconductance value, and a capacitance value, for said filter circuitintegrated within said single-chip multi-band RF receiver based on saidgenerated filter control signal.
 46. The system according to claim 45,wherein said one or more circuits enable modification of a cut-offfrequency for said filter circuit integrated within said single-chipmulti-band RF receiver based on said adjusting one of both of saidtransconductance value, and said capacitance value.
 47. The systemaccording to claim 37, wherein said filter circuit integrated withinsaid single-chip multi-band RF receiver comprises a low-pass filter. 48.The system according to claim 47, wherein said low-pass filter comprisesa Chebyschev filter.